Design of Area and Power Efficient 5:2 Compressor for High Speed Multipliers
نویسنده
چکیده
The paper proposes architectures of 5:3 compressor designs for low power multiplication purposes. The architecture explores the essence of two transistor multiplexer design and novel two transistor XOR gates for the proposed topology with least number of transistors for logic level implementation. The modified and proposed compressor designs reduce the stage delays, transistor count, PDP (power delay product), EDP (energy delay product) and area by utilizing the combinations of XORXNOR gates, MUX circuits and transistor level implementation contrasted with the conventional designs. Simulation studies have been carried out in 65nm, 90nm, 130nm technologies in
منابع مشابه
Design of a low power high speed 4-2 compressor using CNTFET 32nm technology for parallel multipliers
In this article a low power and low latency 4-2 compressor has been presented. By using modified truth table and Pass Transistor Logic (PTL) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. The proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller activ...
متن کاملDesign of a low power high speed 4-2 compressor using CNTFET 32nm technology for parallel multipliers
In this article a low power and low latency 4-2 compressor has been presented. By using modified truth table and Pass Transistor Logic (PTL) a novel structure has been proposed which outperforms previous designs from the frequency of operation view point. The proposed design method has reduced the total transistor count considerably which will lead to reduced power consumption and smaller activ...
متن کاملFast Multiplication Energy - Efficient 7 : 2 Compressor
In many of digital systems used in like graphical processors, digital signal processors fast parallel multiplication using adder trees are present. Multipliers have attracted lots of researchers’ attention into making high-performance multipliers to consume less power and operate faster. This paper presents efficient implementation of comp ress tree adders on FPGAs. A new 7:2 compr essor archit...
متن کاملDesign and Performance Analysis of Wallace Tree Multiplier Using Different Compressors
This paper presents enhancement in the speed performance of Conventional Wallace tree multiplier by reducing the partial products. Wallace tree multiplier is fabricated using 90nm CMOS technology. In this particular work, we have used 3:2 compressor, 4:2 compressor, 5:2 compressor and carry propagate adder (CPA) to reduce the partial products of conventional Wallace tree multiplier and in compr...
متن کاملModified 32-Bit Shift-Add Multiplier Design for Low Power Application
Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. ...
متن کامل